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256 MB SDRAM

"SDRAM memory stands for short Synchronous DRAM, a type of DRAM that can run at much higher clock speeds than conventional memory. Our 256MB SDRAM Memory  actually synchronizes itself with the CPU's bus and is capable of running at 133 MHz, about three times faster than conventional FPM RAM, and about twice as fast EDO DRAM and BEDO DRAM. SDRAM is replacing EDO DRAM in many newer computers." (www.webopedia.com)

256MB SDRAM (Synchronous DRAM) memory

• 256mb SDRAM
• PC133 Memory (will work in 133MHz, 125MHz, 100MHz, 66MHz FSB)
• SDRAM DIMM
• 32 x 64 (16*8 16 Chip Double Sided, Low Density Memory Upgrade)
• 168 Pin
• CL2 (CAS=2) or CL3 (CAS=3)
• Unbuffered, Non-ECC
• 3.3 Volt
• 30 Day Money Back / Lifetime Warranty

Compatibility note: you can use our SDRAM memory in your PC133 MHz FSB, 100MHz FSB, and 66MHz FSB Motherboards that support 168-Pin DIMMs, basically if you need PC100 SDRAM memory or PC66 this DRAM memory is also good to use on your PC. To find SDRAM memory upgrade compatible with your particular system please see our Memory Configurator.

Memory types like SDRAM, DDR, and Rambus RDRAM are found in most of today's computer memory applications:

• SDRAM - Synchronous Dynamic Random Access Memory;
• RDRAM - Rambus Dynamic Random Access Memory;
• DRAM - Dynamic Random Access Memory;
• RAM - Random Access Memory;
• DDR - Double Data Rate is a type of SDRAM in which data is sent on both the rising and falling edges of clock cycles in a data burst.
• DIMM - Dual in-line Memory Module. This physical property describes a module with signal and power pins on both sides of the board. DIMMs can be any number of pins including 144pin SODIMM SDRAM, 168pin SDRAM memory, and 184pin DDR SDRAM.
• Unbuffered - This is the most common configuration for memory. These modules do not use any supporting TTL logic.
• ECC - Error Correcting Code. Logic designed to detect and correct memory errors. Memory modules designed with 72 bits of memory support the motherboard's ECC function.
• Registered - Registers delay memory information for one clock cycle to ensure all communication from the chipset is collected by the clock edge, providing a controlled delay on heavily loaded memories. This allows you to installed four or more modules or larger memory sizes in your application. Registered and non-registered memory can not be mixed.